Total 15 job vacancies by Realtek Singapore Private Limited

JOB DESCRIPTION

· Work with system engineers on timing requirements and feedback on optimization.

· Work on SoC timing constraint, synthesis and timing closure.

· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains

· Conduct formal verification for release comparison.

· Support back-end implementation on timing violation analysis and fix.

· Support scan insertion and optimization.

· Support on power structure and power optimization.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Familiar with ASIC design flow

· Experience in logic synthesis, static timing analysis, timing closure

· Good understanding of DFT and Power structure.

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

JOB DESCRIPTION

· Discussion with system engineers on SoC architecture and feedback on optimization.

· Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;

· Discussion with synthesis engineer and back-end engineer on design optimization.

· SoC DFT support;

· SoC verification plan and SoC verification support

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Knowledge of ASIC design flow

· Experience in RTL coding, RTL and gate-level debug

· Understanding of DFT, timing and power requirements

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Knowledge on mixed-signal design would be an advantage.

JOB DESCRIPTION

· Discussion with system engineers on IP requirement and micro architecture.

· Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.

· Support SoC designer on integration, timing constraints and power domain setting.

· Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience in IP development (either control path intensive or data path intensive)

· Knowledge of timing, DFT and power structure.

· Familiar with UNIX/ Linux environment and scripting

· Experience on communication IP and/or video IP development would be advantage.

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Experience on communication IP development would be an advantage

· Experience on video IP development would be an advantage

JOB DESCRIPTION

· Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;

· Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support; SoC verification plan and SoC verification support

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience with ASIC design flow

· Experience in RTL coding, RTL and gate-level simulation, logic synthesis, static timing analysis, timing closure and verification

· Good understanding of DFT

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

JOB DESCRIPTION

· Discussion with system engineers on SoC architecture and feedback on optimization.

· Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;

· Discussion with synthesis engineer and back-end engineer on design optimization.

· SoC DFT support;

· SoC verification plan and SoC verification support

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Knowledge of ASIC design flow

· Experience in RTL coding, RTL and gate-level debug

· Understanding of DFT, timing and power requirements

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Knowledge on mixed-signal design would be an advantage.

JOB DESCRIPTION

· Work with system engineers on timing requirements and feedback on optimization.

· Work on SoC timing constraint, synthesis and timing closure.

· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains

· Conduct formal verification for release comparison.

· Support back-end implementation on timing violation analysis and fix.

· Support scan insertion and optimization.

· Support on power structure and power optimization.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Familiar with ASIC design flow

· Experience in logic synthesis, static timing analysis, timing closure

· Good understanding of DFT and Power structure.

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.

• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.

• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working

• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.

• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment

JOB REQUIREMENTS

· BSEE or MSEE, entry level

· Strong communication, analytical and documentation skills and ability to interface with other groups

· Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products

· Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/ UVM experience

· Familiar with ASIC verification methodology, tools, and development flow

· Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals

JOB DESCRIPTION

· Discussion with system engineers on IP requirement and micro architecture.

· Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.

· Support SoC designer on integration, timing constraints and power domain setting.

· Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience in IP development (either control path intensive or data path intensive)

· Knowledge of timing, DFT and power structure.

· Familiar with UNIX/ Linux environment and scripting

· Experience on communication IP and/or video IP development would be advantage.

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Experience on communication IP development would be an advantage

· Experience on video IP development would be an advantage

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.

• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.

• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working

• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.

• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment

JOB REQUIREMENTS

· BSEE or MSEE, entry level

· Strong communication, analytical and documentation skills and ability to interface with other groups

· Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products

· Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/ UVM experience

· Familiar with ASIC verification methodology, tools, and development flow

· Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals

JOB DESCRIPTION

· Discussion with system engineers on SoC architecture and feedback on optimization.

· Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;

· Discussion with synthesis engineer and back-end engineer on design optimization.

· SoC DFT support;

· SoC verification plan and SoC verification support

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Knowledge of ASIC design flow

· Experience in RTL coding, RTL and gate-level debug

· Understanding of DFT, timing and power requirements

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Knowledge on mixed-signal design would be an advantage.

JOB DESCRIPTION

· Discussion with system engineers on IP requirement and micro architecture.

· Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.

· Support SoC designer on integration, timing constraints and power domain setting.

· Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience in IP development (either control path intensive or data path intensive)

· Knowledge of timing, DFT and power structure.

· Familiar with UNIX/ Linux environment and scripting

· Experience on communication IP and/or video IP development would be advantage.

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Experience on communication IP development would be an advantage

· Experience on video IP development would be an advantage

JOB DESCRIPTION

· Work with system engineers on timing requirements and feedback on optimization.

· Work on SoC timing constraint, synthesis and timing closure.

· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains

· Conduct formal verification for release comparison.

· Support back-end implementation on timing violation analysis and fix.

· Support scan insertion and optimization.

· Support on power structure and power optimization.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Familiar with ASIC design flow

· Experience in logic synthesis, static timing analysis, timing closure

· Good understanding of DFT and Power structure.

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.

• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.

• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working

• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.

• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment

JOB REQUIREMENTS

· BSEE or MSEE, entry level

· Strong communication, analytical and documentation skills and ability to interface with other groups

· Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products

· Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/ UVM experience

· Familiar with ASIC verification methodology, tools, and development flow

· Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals

JOB DESCRIPTION

· Discussion with system engineers on IP requirement and micro architecture.

· Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.

· Support SoC designer on integration, timing constraints and power domain setting.

· Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience in IP development (either control path intensive or data path intensive)

· Knowledge of timing, DFT and power structure.

· Familiar with UNIX/ Linux environment and scripting

· Experience on communication IP and/or video IP development would be advantage.

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Experience on communication IP development would be an advantage

· Experience on video IP development would be an advantage

JOB DESCRIPTION

· Work with SoC Integration and SoC Timing on power structure optimization

· Work on UPF development to support different stages of implementation flow and SoC verification

· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains

· Conduct power structure check at different implementation stages.

· Support back-end implementation on power structure and optimization.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Familiar with ASIC design flow

· Experience in UPF development and power check.

· Good understanding of Power structure.

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills