Total 4 Art / Design / Entertainment job vacancies in IRL - Cork, Ringaskiddy

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title:                                             Design Engineering Director

Location:                                             Cork/Dublin

Reports to:                                         Senior Design Engineering Group Director

Job Overview:

Cadence Design Systems is looking for a design engineering director to lead and develop our new and exciting ultra-high speed controller IP developments.

Previous IEEE 802.3 ethernet experience desired but not essential. 

You will be technically leading the ethernet IP and subsystem design/verification team as we develop solutions for the latest 802.3 200G,400G,800G and 1.6T ethernet standards. 

In addition to controller IP developments, there is a parallel requirement to collaborate with the Cadence high speed SerDes teams in order to produce full ethernet subsystems and solutions for our customers.

Job Qualifications

• Previous experience developing and building teams to realize business goals, proving line management and support to complete hiring needs.
• Extensive protocol knowledge in key protocols such as DDR, PCIe, CXL, UCIe, Ethernet, Flash Storage etc.
• Ability to architect SOC/NOC based solutions, within a team, providing direction and leadership to extended team.
• Extensive RTL implementation knowledge, including full design flow knowledge from Marketing requirements document (MRD) to completing GDSII based solution.
• Extensive design flow knowledge so we can provide the most efficient flows to meet business goals, including Synthesis, Constraint development, LINT, Clock domain crossing (CDC)
• Extensive knowledge in Metric Driven Verification (MDV) and Formal techniques, which are a nice to have.
• Knowledge of Hardware and emulation techniques are a nice to have.
• Knowledge of how to best utilize cloud-based computing solutions, configuration management and associated farms to again provide most efficient solutions.

Education/Experience

• Honors Degree BSc and or MSc in Electronics Computer Science course or equivalent.
• Minimum 20 Years industry experience.

Additional Skills/Preferences:                     

• Ability to manage a technical team of up to 12 people and drive teams towards a set of defined goals and roadmaps.
• Ability to assess product development and work with marketing to define roadmap that satisfies customers’ needs.
• Ability to report to and advise upper management.
• Ability to travel and support internal strategic business development meetings and external customer-based meetings.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job  Responsibilities:

• Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)
• Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
• Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections
• Participate in technical leadership of the team in the areas of circuit design and SERDES architectures
• Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications:

• Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development
• Working knowledge of a set of common SERDES standards and their electrical requirements
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• BEng, MEng or PhD

Additional Skills/Preferences:           

• Cadence tool experience and design experience at >10Gbps and in <40nm technologies
• Lab test experience as part of silicon evaluation is advantageous
• Interest in publishing academic papers and presenting at conferences e.g. ISSCC, JSSC

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title:                                             Principal Analog Mixed Signal Design Engineer (Memory/Audio Interface)

Location:                                             Cork

Reports to:                                         Senior Design, Engineering Group Director

Job Overview:

Lead Analog and Mixed Signal design of high speed memory interface analog components used in state-of-the-art DDR memory interface PHYs in leading edge technology nodes.  Consisting of blocks such as IOs, amplifiers, comparators, drivers, duty cycle correctors, PLLs, DLLs, level shifters, etc. in advanced IC nodes in volume production.

As Principal Design Engineer, you will provide technical direction and coordination to the analog IC design team and Identify opportunities to advance technology of analog design and participate in strategic internal analog IP development.

Job Responsibilities:

• Design of High-Speed memory interface products at data rates up to and exceeding 36 Gbps on leading edge technology nodes (e.g. 5nm FinFET CMOS)
• Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
• Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections
• Work with Technical Team Leads in the areas of circuit design and architects
• Mentor Junior Design Engineers when the project need arises
• Work with global teams (US, India, China, EU), which work in different time-zones

Job Qualifications:

• Successful candidate should be BEng, MEng qualified or have an equivalent qualification.
• Minimum of 4 years of CMOS design experience, preferably in the area of CMOS SERDES, DDR or high-speed I/O IC design
• Should have a good understanding of jitter and signal equalization techniques
• Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification
• Cadence tool experience and design experience in <40nm technologies preferred.
• Lab test experience as part of silicon evaluation is advantageous

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 

We’re doing work that matters. Help us solve what others can’t.

 ROLE SUMMARY 

The Digital Manufacturing (DM) Team’s mission is to simplify processes and experiences to drive Pfizer Global Supply (PGS) outcomes. DM is responsible for the digital transformation of all processes across the shop floor, quality control, quality assurance, engineering, environment, health, and safety operations. DM drives end-to-end operations efficiencies by embedding artificial intelligence's predictive and prescriptive insights into our manufacturing, quality, and cross-functional applications. Our team philosophy is “Do good work” and as per Pfizer’s Purpose Blueprint, “Win the Digital Race in Pharma.” 

Our team, Experience Design and Business Adoption (xD & BA), consists of two main groups under which our disciplines are divided across; Experience Design consisting of Design Research, Design Strategy, Product Design, Design Engineering and Design Ops; and Business Adoption which includes Trainings, Communications and Change Management. We support PGS Digital Manufacturing solutions by using collaborative methods with a human-centered focus to deliver solutions to our PGS colleagues ranging from shop floor operators to executive suite. 

As a Product Design Manager, you will define concepts, establish strategies, get hands on, as well as manage the consistent delivery of design artifacts that unify our solutions and services. You will be collaborating with solution and product owners, developers, agile leads, domain leaders, and other xD & BA team members. 

ROLE RESPONSIBILITIES  

The ​Product Design Manager, Experience Design​  colleague’s responsibilities include but are not limited to: 

• Support design teams to scope initiatives, identify priorities, form clear and concise design project plans, and deliver projects that have multiple stakeholders and moving parts within an Agile framework. 

• Guide the design process from framing a challenge to, visualising research insights, concepts, UI design and support implementation. 

• Contribute to the vision and strategy of uniting all solutions under a common set of design practices, design standards, and visual language. 

• Lead design projects across the entire solution lifecycle and multiple launches that may begin in one platform and continue or end on another. 

• Collaborate with researchers, engineers, solution owners, designers, and other stakeholders to synthesize data from multiple sources to communicate insights or recommendations in compelling and creative ways. 

• Create deliverables including sketches, high fidelity UI designs, prototypes, proof of concepts, wireframes, user flows, user stories, and information architecture .

• Delegate and oversee project tasks carried out by junior team members, helping them to develop their individual strengths and skillsets. 

• Lead meetings with global stakeholders to develop detailed briefs and clarify design requirements. 

• Help continuously develop and enhance our team by taking ownership for accomplishing new and different requests; exploring opportunities to add value to organizational accomplishments. 

• Partner with consulting partners to manage overall project execution, providing coaching and feedback where necessary. 

• Interact withstakeholders throughout the duration of projects with a high degree of polish, professionalism, and reliability to ensure needs are met, changes are incorporated, and deliverables exceed expectations. 

• Track design project performance, specifically to analyze the successful completion of short- and long-term goals. 

BASIC QUALIFICATIONS  

• 5+ years related experience in Product, Service, Interaction Design, or similar role 

• A solid understanding and demonstration of user centric design principles 

• An advanced proficiency with design and prototyping tools primarily Figma 

• Ability to collaborate actively as part of a multi-disciplinary, multi-cultural and multi-location teams 

• Enthusiasm, patience, and a solutions-oriented attitude toward any risks and challenges 

• Comfort with ambiguity and complex problems  

• Organized, able to act independently, and able to switch between different projects in a fast-paced environment 

• Familiarity in emergent technologies and how to apply them to different business challenges 

• Ability to confidently present work and to accept or provide constructive feedback 

• Experience utilizing Lean and Agile methodologies 

• Bachelor's Degree in Design or relevant field  

PREFERRED QUALIFICATIONS 

• UX, HFI, SAFe or equivalent certification highly desirable  

• Strong visual design skills 

• Working knowledge of HTML, CSS, and JavaScript frameworks a plus 

• Pharmaceutical or Manufacturing Industry experience a plus 

PHYSICAL/MENTAL REQUIREMENTS 

Ability to manage many parallel objectives and changing priorities. Working with various stakeholders from multiple groups. 

NON-STANDARD WORK SCHEDULE, TRAVEL OR ENVIRONMENT REQUIREMENTS  

Occasional Travel to Grange Castle Location may be required  

Post pandemic – 10% occasional business travel 

Make a difference today! All suitable candidates should apply through the link with CV provided. We are looking forward to hearing from you!

In order to be considered for this position you need to be legally eligible to work in the EU.

Pfizer is an equal opportunity employer and complies with all applicable equal employment opportunity legislation in each jurisdiction in which it operates.

Due to the high volume of applications we will be contacting successful candidates only.