Total 18 art design entertainment job vacancies in us la new orleans 6 canal street fillmore new orleans

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.
  

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. 2 years of relevant experience in similar field.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

What you do

Be part of the team that validates the physical sign-off of our chips, powering the brands we love every year with 2 billion consumer electronic products such as digital TVs, home audio devices, DVD/Blue-ray players, smartphones, tablets, networking and connectivity products, and many more. As a member of the MediaTek Physical Verification Sign-off team, you will be responsible for ensuring the manufacturability and reliability of IC designs through rigorous physical verification processes to enable the success of our chips tape-out. Join us in shaping the future of technology and making a real impact on the world!

• Responsible for assembling of various design system into a full chip.
• Perform design rule checking (DRC) to identify and resolve System-on-chip layout violations and ensure compliance with manufacturing rules and constraints.
• Conduct layout versus schematic (LVS) verification to ensure the accuracy and consistency between full chip layout and schematic of the IC design.
• Execute electrical rule check (ERC) to identify potential electrical issues and ensure the integrity of the design.
• Perform antenna and electrostatic discharge (ESD) checks to prevent potential reliability, latch-up, leakage issues.
• Collaborate with design and layout teams to address and resolve physical design issues and optimize the layout for manufacturability and reliability.
• Contribute to the development and improvement of physical verification methodologies and flows.
• Work closely with process technology teams to understand and address process-related challenges and constraints.
• Participate in tape-out activities and ensure that the physical design meets the required quality and reliability standards for fabrication.

What you bring

• Bachelor/master’s degree in Electrical/Electronic Engineering / Computer Science or equivalent
• With minimum 4 years of relevant experience
• Solid understanding of physical design concepts, IC manufacturing processes, and semiconductor device physics.
• Proficiency in using physical verification tools such as Calibre, IC Validator, or other industry-standard DRC/LVS tools.
• Experience with scripting languages such as TCL, Perl, or Python for automation and tool customization.
• Strong problem-solving skills and the ability to analyze and debug complex physical design issues.
• Excellent communication and teamwork skills to collaborate effectively with cross-functional teams.
• Familiarity with EDA (Electronic Design Automation) tools and design methodologies is a plus.
• Proficient in UNIX (Linux) platforms
• Strong communication skills, problem solving and analytical skills
• Candidate with more years of experience will be considered for a more Senior role.

Location: One North, Singapore

Who We Are

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

What you will do

• APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
• Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
• Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO

What you bring

• Apr hands on for n5/n4/n3e process using Innovus and Fusion compiler EDA tool
• tcl/csh/perl/bash. programming skill
• Timing Analysis Debugging and Fixing skills
• Experienced N4/N3e process

What you do

Be part of the team that validates the physical sign-off of our chips, powering the brands we love every year with 2 billion consumer electronic products such as digital TVs, home audio devices, DVD/Blue-ray players, smartphones, tablets, networking and connectivity products, and many more. As a member of the MediaTek Physical Verification Sign-off team, you will be responsible for ensuring the manufacturability and reliability of IC designs through rigorous physical verification processes to enable the success of our chips tape-out. Join us in shaping the future of technology and making a real impact on the world!

• Responsible for assembling of various design system into a full chip.
• Perform design rule checking (DRC) to identify and resolve System-on-chip layout violations and ensure compliance with manufacturing rules and constraints.
• Conduct layout versus schematic (LVS) verification to ensure the accuracy and consistency between full chip layout and schematic of the IC design.
• Execute electrical rule check (ERC) to identify potential electrical issues and ensure the integrity of the design.
• Perform antenna and electrostatic discharge (ESD) checks to prevent potential reliability, latch-up, leakage issues.
• Collaborate with design and layout teams to address and resolve physical design issues and optimize the layout for manufacturability and reliability.
• Contribute to the development and improvement of physical verification methodologies and flows.
• Work closely with process technology teams to understand and address process-related challenges and constraints.
• Participate in tape-out activities and ensure that the physical design meets the required quality and reliability standards for fabrication.

What you bring

• With minimum 8 years of relevant experience.tronic Engineering / Computer Science or equivalent..
• With minimum 8 years of relevant experience
• Solid understanding of physical design concepts, IC manufacturing processes, and semiconductor device physics.
• Proficiency in using physical verification tools such as Calibre, IC Validator, or other industry-standard DRC/LVS tools.
• Experience with scripting languages such as TCL, Perl, or Python for automation and tool customization.
• Strong problem-solving skills and the ability to analyze and debug complex physical design issues.
• Excellent communication and teamwork skills to collaborate effectively with cross-functional teams.
• Familiarity with EDA (Electronic Design Automation) tools and design methodologies is a plus.
• Proficient in UNIX (Linux) platforms.
• Strong communication skills, problem solving and analytical skills.

Location: One North, Singapore

Who We Are

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

At Mediatek’s Memory Design Automation team, we work seamlessly with worldwide memory design team to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow.

Responsibility

1. Responsible for cutting edge technology node’s SRAM compiler design and deliver best quality of design kit.
2. Seamlessly collaborate with SRAM design and layout team to achieve highest quality of design kit delivery.
3. Responsible for data analysis and platform development of memory usage big data.
4. Responsible for physical verification (DRC/ERC/LVS/ANT/PERC) on SRAM compiler.
5. Responsible for spice simulation on timing, power and noise on SRAM compiler.
6. Responsible for QA check and development on SRAM compiler.

Requirements

1. Bachelor or Master Degree in Electrical and Electronic Engineering or Computer Engineering or Computer Science.
2. Multi-task capability and strong self-driven characteristics to meet challenging schedule.
3. Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
4. Strong interpersonal skills to work with team members with multi-cultural environment
5. Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
6. Candidate with experience is preferable.

Location: One North, Singapore

Why MediaTek?

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

Mediatek’s Memory Design Automation team is looking for fresh talent to join us as a modeling engineer for the development of behavioral, FPGA, timing and DFT simulation models. The role will be required to create, debug and optimize SRAM models for ASIC design flow.

The candidate must be a team player, able to communicate clearly and concisely to deliver quality work on time.

About the team:

The Mediatek’s Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness.

What you do:

• Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow.
• Develop automation flow and scripts with Perl or Python.
• Execute EDA tools from vendors such as Synopsys, Mentor to verify models’ correctness.
• Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance.
• Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions.

What you bring:

• Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related discipline with at least 3 years of semiconductor industry experience.
• Have at least 3 years experience using Linux systems.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Good understanding of upf and system verilog.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required
• Experience with EDA tools will be helpful:

o DFT: Logicvision, Tessent, Fastscan

o Synthesis: Design compiler, Genus

o Simulation tools:VCS, QuestaSim, NC

o STA tools such as PrimeTime

• Good scripting and flow automation skills, in Perl or Python.
• A team player, meticulous, able to work and learn independently are important attributes for this job.

Location: One North, Singapore

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. of 8 years of relevant verification experiences.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

Job Description

• Working on 6nm and below advanced process project APR and Timing/PI sign-off
• Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros)
• Take the Block or Block coordinator role for complex blocks
• Do early prediction for critical APR/Timing/PI issues

Job Requirements

• APR/Timing/PI hands-on/tapeout experience on complicated hierarchical chip
• TCL/Perl/Python/C/C++ programming skill
• Have advanced process(n6 or below) experience is a plus
• Excellent communication and team work spirit

Job Description

• Working on 6nm and below advanced process project APR and Timing/PI sign-off
• Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros)
• Take the Block or Block coordinator role for complex blocks
• Do early prediction for critical APR/Timing/PI issues

Job Requirements

• APR/Timing/PI hands-on/tapeout experience on complicated hierarchical chip
• TCL/Perl/Python/C/C++ programming skill
• Have advanced process(n6 or below) experience is a plus
• Excellent communication and team work spirit

Job description:

• Design Engineer for embedded memory design and verification in advanced nodes for high performance ASIC targeting Cloud AI/ Data Center Network Switch and 5G infrastructure, CPU and AP-SOC
• Collaborate closely with product and architecture teams to define, design and develop high performance customized semiconductor memories to meet PPA specifications and integration.
• Innovate, design, and incorporate special circuits and methodology to achieve best-in-class PPA for custom and compiler memories.
• Develop timing/power/noise characterization flow for advanced node memory compiler. Strong focus on design automation for SRAM compiler, big data analysis and design verification
• Develop memory analysis flow for PPA check

Job requirements:

• 3+ years of hands on experience in design of embedded memories (SRAM, TCAM) for high performance processors or ASICs in advanced nodes (3nm/5nm)
• Good understanding of Digital Circuit design techniques in FinFet technologies.
• Exposure to complete design cycle of SRAM memory and compiler development
• Supervise layout engineers and review layout for optimality.
• Experience in using industry standard schematic entry tools, advanced transistor level simulators (XA, HSIM, FINESIM)
• Experience with LEC tools (ESPCV)
• Knowledge of RTL and place and route tools is a plus
• Ability to come up with design verification and test plans
• Silicon debug and bring up experience is a plus
• Working knowledge of scripting in Perl/Python
• Willingness to collaborate closely with cross functional teams across the globe

The Job

• Develop timing/power/noise characterization flow for advanced node memory compiler.
• Strong focus on design automation for SRAM compiler, big data analysis and design verification.
• Develop memory analysis flow for PPA check.

The Talent

• Bachelor's Degree (with min. 6 years of relevant industry experience) /Masters Degree (with min. 4 years of relevant industry experience)/ PhD in Electrical and Electronic Engineering/Computer Engineering/Computer Science.
• Knowledge of SRAM/ROM memory functionality and high speed, low power memory design architecture.
• Experience in spice simulation and understand CMOS layout view, Verilog coding is preferable.
• Proficient in script programming with Perl or Python3.

What you will do

• Responsible for standard cell test key design of leading-edge process node (4nm/3nm/2nm), from schematic netlist to gds.
• Work with layout engineer for test key implementation and physical verification including DRC/LVS/ERC/ANT.
• Perform layout extraction, simulation, testing data collection and processing.
• Analyze simulation and silicon data including performance, power correlation, big data analysis, AI model training.
• Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks.
• Develop advanced library generation methodology and flow, including timing & power characterization, kit generation, regression, and quality assurance, involved with data analysis and machine learning as well.

What you bring

• BS/MS in Electrical and Electronic Engineering/Computer Engineering/Computer Science with minimum 8 years(MS) or 10 years(BS) industry experience.
• Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge.
• Experience of test chip design in FinFet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills.
• Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning.
• Strong communication and teamwork skills to collaborate effectively with cross-functional teams.

Location: One North, Singapore

What you will do

[Physical Design]

• Work for physical design and development activities of MediaTek’s Ghz ARM-based microprocessors
• Involve in activities encompass physical design and analysis of complex and timing-critical microprocessor partition blocks and
• Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing and power optimization

[STA/Power Signoff]

• Involve in activities encompass Static Timing Analysis on advanced process nodes (28nm, 20nm, 16nm & beyond)
• Technical disciplines include STA, and analysis of complex and timing-critical microprocessor
• Work closely with RTL function designers and physical designers to optimize design components such as timing and power
• Design Methodology (1):
• This position is in charge of design methodology from RTL-Synthesis-DFT-PNR-STA-PI.
• Specific skill set is: able to boost productivity using either programming or EDA solution
• AI learning Programming is a big plus

What you will bring

• Bachelor/Masters Degree in Electrical and Electronic Engineering/Computer Engineering
• Good with concept of digital design
• Good with communication, team work and scripting skills
• Understanding of RTL2GDS flow is a plus

Location: One North, Singapore

What you will do

[Physical Design]

• Work for physical design and development activities of MediaTek’s Ghz ARM-based microprocessors
• Involve in activities encompass physical design and analysis of complex and timing-critical microprocessor partition blocks and
• Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing and power optimization

[STA/Power Signoff]

• Involve in activities encompass Static Timing Analysis on advanced process nodes (28nm, 20nm, 16nm & beyond)
• Technical disciplines include STA, and analysis of complex and timing-critical microprocessor
• Work closely with RTL function designers and physical designers to optimize design components such as timing and power
• Design Methodology (1):
• This position is in charge of design methodology from RTL-Synthesis-DFT-PNR-STA-PI.
• Specific skill set is: able to boost productivity using either programming or EDA solution
• AI learning Programming is a big plus

What you will bring

• Bachelor/Masters Degree in Electrical and Electronic Engineering/Computer Engineering
• Good with concept of digital design
• Good with communication, team work and scripting skills
• Understanding of RTL2GDS flow is a plus

Location: One North, Singapore